? semiconductor components industries, llc, 2002 august, 2002 rev. 0 1 publication order number: and8086/d and8086/d board mounting notes for quad flat-pack no-lead package (qfn) introduction various on semiconductor components are packaged in an advanced quad flatpack nolead package (qfn). because the qfn platform represents the latest in surface mount packaging technology, it is important that the design of the printed circuit board (pcb), as well as the assembly process, follows the suggested guidelines outlined in this document. qfn package overview the qfn platform offers a versatility which allows either a single or multiple semiconductor devices to be connected together within a leadless package. this packaging flexibility is illustrated in figure 1 where four devices are packaged together with a custom pad configuration. figure 1. the underside of a 4chip qfn package figure 2, illustrates how the package height is reduced to a minimum by having the both the die and wirebond pads on the same plane. when mounted, the leads are directly attached to the board without a spaceconsuming standoff which is inherent in a leaded package. figure 2 also illustrates how the ends of the leads are flush with the edge of the package. this configuration allows for the maximum die size within a given footprint, while maximizing the board space efficiency. die leadframe wirebond figure 2. crosssection of a singledevice qfn package in addition to these features, the qfn package has excellent thermal dissipation and reduced electrical parasitics due to its efficient and compact design. printed circuit board design considerations smd and nsmd pad configurations there are two different types of pcb pad configurations commonly used for surface mount leadless qfn style packages. these different i/o configurations are: 1. non solder masked defined (nsmd) 2. solder masked defined (smd) as their titles describe, the nsmd contact pads have the solder mask pulled away from the solderable metallization, while the smd pads have the solder mask over the edge of the metallization, as shown in figure 3. with the smd pads, the solder mask restricts the flow of solder paste on the top of the metallization which prevents the solder from flowing along the side of the metal pad. this is different from the nsmd configuration where the solder will flow around both the top and the sides of the metallization. figure 3. nsmd and smd pad configurations solder mask opening solder mask overlay solderable pad nsmd smd application note http://onsemi.com
and8086/d http://onsemi.com 2 typically, the nsmd pads are preferred over the smd configuration since defining the location and size of the copper pad is easier to control than the solder mask. this is based on the fact that the copper etching process is capable of a tighter tolerance than the solder masking process. in addition, the smd pads will inherently create a stress concentration point where the solder wets to the pad on top of the lead. this stress concentration point is eliminated when the solder is allowed to flow down the sides of the leads in the nsmd configuration. nsmd pad configurations when dimensionally possible, the solder mask should be located at least a 0.076 mm (0.003 in) away from the edge of the solderable pad. this spacing is used to compensate for the registration tolerances of the solder mask, as well as to insure that the solder is not inhibited by the mask as it reflows along the sides of the metal pad. the dimensions of the pcb's solderable pads should match those of the pads on the package as shown in figure 4. the 1:1 ratio between the package's pad configuration, and that of the pcb's, is desired for optimal placement accuracy and reliability. qfn board mounting process the qfn board mounting process is optimized by first defining and controlling the following processes: 1. creating and maintaining a solderable metallization on the pcb contacts 2. choosing the proper solder paste 3. screening/stenciling the solder paste onto the pcb 4. placing the package onto the pcb 5. reflowing the solder paste 6. final solder joint inspection recommendations for each of these processes are located below. pcb solderable metallization there are two commonly plated solderable metallizations which are used for pcb surface mount devices. in either case, it is imperative that the plating is uniform, conforming, and free of impurities to insure a consistent solderable system. the first metallization consists of an organic solderability preservative coating (osp) over the copper plated pad. the or ganic coating assists in reducing oxidation in order to preserve the copper metallization for soldering. the second recommended solderable metallization consists of plated electroless nickel over the copper pad, followed by immersion gold. the thickness of the electroless nickel layer is determined by the allowable internal material stresses and the temperature excursions the board will be subjected to throughout its lifetime. even though the gold metallization is typically a selflimiting process, the thickness should be at least 0.05 m thick, and not consist of more than 5% of the overall solder volume. having excessive gold in the solder joint can create gold embitterment which may affect the reliability of the joint. solder type solder paste such as cookson electronics' ws3060 with a type 3 or smaller sphere size is recommended. the ws3060 has a watersoluble flux for cleaning. cookson electronics' omnix 5000 can be used if a noclean flux is preferred. a b c d e pcb board design a b c d e qfn package outline figure 4. printed circuit board layout using nonsolder masked defined i/o pads
and8086/d http://onsemi.com 3 solder screening onto the pcb stencil screening the solder onto the pcb board is commonly used in the industry. the recommended stencil thickness used is 0.075 mm to 0.127 mm (0.003 in to 0.005 in) and the sidewalls of the stencil openings should be tapered approximately 5 degrees to facilitate the release of the paste when the stencil is removed from the pcb. for a typical edge pcb terminal pad, the stencil opening should be the same size as the pad size on the package. however, in cases where the die pad is soldered to the pcb, the stencil opening must be divided into smaller cavities as shown in figure 5. dividing the larger die pads into smaller screen openings reduces the risk of solder voiding and allows the solder joints for the smaller terminal pads to be at the same height as the larger ones. package placement onto the pcb pick and place equipment with the standard tolerance of 0.05 mm or better is recommended. the package will tend to center itself and correct for slight placement errors during the reflow process due to the surface tension of the solder. solder reflow once the package is placed on the pc board along with the solder paste, a standard surface mount reflow process can be used to mount the part. figure 6 is an example of a standard reflow profile. the exact profile will be determined, and is available, by the manufacture of the paste since the chemistry and viscosity of the flux matrix will vary. these variations will require small changes in the profile in order to achieve an optimized process. in general, the temperature of the part should be raised not more than 2 c/sec during the initial stages of the reflow profile. the soak zone then occurs when the part is approximately 150 c and should last for 30 to 120 seconds. typically, extending the time in the soak zone will reduce the risk of voiding within the solder. the temperature is then raised and will be above the liquidus of the solder for 30 to 100 seconds depending on the mass of the board. the peak temperature of the profile should be between 20 c and 225 c for eutectic sn/pb solder. if required, removal of the residual solder flux can be completed by using the recommended procedures set forth by the flux manufacturer. solder stencil design pcb pad outline die attach pad die attach pad figure 5. solder stencil design illustrating how stencil openings are divided into an array for large die pads 0.984 1.270 pitch 16 x 0.458 0.744 0.744 32x sq. 16 x 0.458 1.270 pitch 16 x 1.210 16 x 1.210 time (sec) figure 6. typical reflow profile for eutectic tin/lead solder 0 50 100 150 200 250 0 100 200 300 400 500 temperature ( c) peak of 225 c soak zone (30 to 120 sec) time above liquidus 183 less than 2 c/sec
and8086/d http://onsemi.com 4 final solder inspection the inspection of the solder joints is commonly performed with the use of an xray inspection system. with this tool, one can locate defects such as shorts between pads, open contacts, voids within the solder as well as any extraneous solder. in addition to searching for defects, the mounted device should be rotated on its side to inspect the sides of the solder joints with an xray inspection system. the solder joints should have enough solder volume with the proper standoff height so that an ahour glasso shaped connection is not formed as shown below in figure 7. ahour glasso solder joints are a reliability concern and must be avoided. figure 7. side view of qfn illustrating preferred and undesirable solder joints pcb preferred solder joint undesirable ahour glasso solder joint rework procedure due to the fact that the qfn is a leadless device, the entire package must be removed from the pc board if there is an issue with the solder joints. it is important to minimize the chance of overheating neighboring devices during the removal of the package since the devices are typically in close proximity with each other. standard smt rework systems are recommended for this procedure since the airflow and temperature gradients can be carefully controlled. it is also recommend that the pc board be placed in an oven at 125 c for 4 to 8 hours prior to heating the parts to remove excess moisture from the packages. in order to control the region which will be exposed to reflow temperatures, the board should be heated to 100 c by conduction through the backside of the board in the location of the qfn. typically, heating nozzles are then used to increase the temperature locally. once the qfn's solder joints are heated above their liquidus temperature, the package is quickly removed and the pads on the pc board are cleaned. the cleaning of the pads is typically performed with a bladestyle conductive tool with a desoldering braid. a no clean flux is used during this process in order to simplify the procedure. solder paste is then deposited or screened onto the site in preparation of mounting a new device. due to the close proximity of the neighboring packages in most pc board configurations, a miniature stencil for the individual component is typically required. the same stencil design that was originally used to mount the package can be applied to the ministencil for redressing the pad. due to the small pad configurations of the qfn, and since the pads are on the underside of the package, a manual pick and place procedure without the aid of magnification is not recommended. a dual image optical system where the underside of the package can be aligned to the pc board should be used instead. reflowing the component onto the board can be accomplished by either passing the board through the original reflow profile, or by selectively heating the qfn with the same process that was used to remove it. the benefit with subjecting the entire board to a second reflow is that the qfn's will be mounted consistently and by a profile that is already defined. the disadvantage is that all of the other devices mounted with the same solder type will be reflowed for a second time. if subjecting all of the parts to a second is either a concern or unacceptable for a specific application, than the localized reflow option would be the recommended procedure. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 291 kamimeguro, meguroku, tokyo, japan 1530051 phone : 81357733850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8086/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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